A conventional technology related to the present invention is described in Japanese Patent Unexamined Publication No. 2003-318398. According to this technology, an N-type polycrystalline silicon layer and an N+-type polycrystalline silicon layer are formed adjacently to each other on a main surface of a semiconductor body composed of an N+-type silicon carbide substrate with an N−-type silicon carbide epitaxial region formed thereon. The epitaxial region forms heterojunctions with the N-type polycrystalline silicon layer and the N+-type polycrystalline silicon layer. Moreover, a gate electrode is formed adjacently to the junction portion of the epitaxial region with the N+-type polycrystalline silicon layer, with a gate insulating film provided therebetween. The N-type polycrystalline silicon layer is connected to a source electrode, and a drain electrode is formed on the back face of the N+-type silicon carbide substrate.
In a conventional method of manufacturing such a semiconductor device, a resist mask is formed on a polycrystalline silicon layer, and an impurity dopant is doped into an opening portion. Thereafter, the resist mask is removed once, and another resist mask having an opening provided with an inward offset with respect to the impurity-doped region is formed again. Then, etching is performed.